1. Field of the Invention
The present invention relates to a semiconductor non-volatile memory device and, more particularly, to a memory device in which a non-volatile memory cell using a floating gate circuit element, for example, an electrically erasable and programmable read only memory (EEPROM) cell, is provided at each intersection of a plurality of word lines and a plurality of bit lines.
As one form of the semiconductor non-volatile memory device, a non-volatile random access memory (NVRAM) device is known in which a volatile memory cell, for example, a static RAM (SRAM) cell, and an EEPROM cell are combined on a one-to-one basis on a chip and integrated. Since such an NVRAM device possesses both a function of an SRAM, i.e., a high speed read/write operation, and a feature of an EEPROM, i.e., non-volatility, it has been utilized in fields in which, even when a power source is OFF, data is not lost but stored, and when the power source is ON, the data can be freely erased and programmed. For example, the NVRAM device is utilized in electronic musical instruments, IC cards, facsimile apparatuses, telephone sets, or the like.
2. Description of the Related Art
In the conventional NVRAM device, the store operation is carried out by utilizing a tunnel effect occurring within an oxidation layer formed between a floating gate and a diffused region in the EEPROM cell. In the store operation, a strongly boosted voltage is employed and a portion thereof is applied across a tunnel capacitor representing an equivalent capacitance of the oxidation layer, with the result that positive or negative charges remain on the floating gate. For example, the positive charges correspond to "1" data and the negative charges to "0". Namely, to reliably carry out the store operation for each memory cell, a predetermined high voltage must be fed to every cell.
In the known non-volatile memory device, a power supply line for feeding or transmitting the high voltage is commonly connected to all of the cells, and therefore, where a leak occurs in any one of the cells due to the destruction or deterioration of the tunnel capacitor or the like, currents flow through the non-functional cell, so that the high level of the voltage is lowered as a whole. As a result, a sufficiently high voltage required for storing data cannot be obtained even in a functional cell where a cell leak does not occur, and this is not preferable from the viewpoint of the reliability of the store operation.
Also, it is known that, when the store and recall operations are repeated, a memory cell may become non-functional due to fatigue of the oxidation layer or the like, and in this case, a wrong data is read out from the non-functional cell. Accordingly, a device has been proposed in which a circuit for automatically correcting the wrong data, hereinafter referred to as an error check and correct (ECC) circuit, is mounted on a chip. In this case, the device can function normally only when a one bit cell becomes non-functional.
In the device where a power supply line of the high voltage for the store operation is commonly connected to all of the cells, however, there is a possibility in that all of the functional cells will become non-functional due to only one non-functional cell. In this case, even if the ECC circuit is provided, a perfect correction of all wrong data cannot be obtained.